Here's all the custom chip pinouts. I'm cutting and pasting from my notes so excuse any spelling errors or obvious mistakes.
HuC6280:
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HuC6280 pin assignments
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Pin Signal Dir
1 - A5 o Address bit 5
2 - A4 o Address bit 4
3 - A3 o Address bit 3
4 - A2 o Address bit 2
5 - A1 o Address bit 1
6 - A0 o Address bit 0
7 - GND s Ground
8 - +5V s Power supply
9 - XOUT o Output for a crystal, not used.
10 - XIN i 21.477270 MHz clock input (OSC1)
11 - /RESET i Reset signal input
12 - RDY i Insert wait state while pulled low
13 - SX o Complementary CPU clock (7.16 or 1.79 MHz)
14 - HSM o High Speed Mode (1= 7.16, 0= 1.78 MHz)
15 - +5V s Ground
16 - GND s Power supply
17 - LOUT o Audio output, left channel
18 - ROUT o Audio output, right channel
19 - VCC s +5V for PSG
20 - VEE s +2.5V for PSG
21 - AGND s Ground for PSG
22 - K0 i Input port K ($1000.D0)
23 - ??? - Has pull-up to +5V. Active high pulses at irregular intervals.
24 - K1 i Input port K ($1000.D1)
25 - K2 i Input port K ($1000.D2)
26 - K3 i Input port K ($1000.D3)
27 - K4 i Input port K ($1000.D4)
28 - K5 i Input port K ($1000.D5)
29 - K6 i Input port K ($1000.D6)
30 - K7 i Input port K ($1000.D7)
31 - O0 o Output port O ($1000.D0)
32 - O1 o Output port O ($1000.D1)
33 - O2 o Output port O ($1000.D2)
34 - O3 o Output port O ($1000.D3)
35 - O4 o Output port O ($1000.D4)
36 - O5 o Output port O ($1000.D5)
37 - O6 o Output port O ($1000.D6)
38 - O7 o Output port O ($1000.D7)
39 - ??? - Always '1'
40 - ??? - Always '1'
41 - ??? - Always '1'
42 - ??? - Always '1'
43 - /IRQ2 i IRQ2 interrupt input
44 - /IRQ1 i IRQ1 interrupt input
45 - /NMI i NMI interrupt input
46 - SYNC o Memory read type; 1= Opcode fetch, 0= Not opcode fetch
47 - +5V s Power supply
48 - GND s Ground
49 - D0 i/o Data bus, bit 0
50 - D1 i/o Data bus, bit 1
51 - D2 i/o Data bus, bit 2
52 - D3 i/o Data bus, bit 3
53 - D4 i/o Data bus, bit 4
54 - D5 i/o Data bus, bit 5
55 - D6 i/o Data bus, bit 6
56 - D7 i/o Data bus, bit 7
57 - +5V s Power supply
58 - GND s Ground
59 - /CEK o HuC6260 /CS (@ FF:0400-07FF)
60 - /CE7 o HuC6270 /CS (@ FF:0000-03FF)
61 - /CER o Work RAM /CS (@ F8-FB:0000-1FFF)
62 - /RD o Memory read strobe
63 - /WR o Memory write strobe
64 - A20 o Address bus, bit 20
65 - A19 o Address bus, bit 19
66 - A18 o Address bus, bit 18
67 - A17 o Address bus, bit 17
68 - A16 o Address bus, bit 16
69 - A15 o Address bus, bit 15
70 - A14 o Address bus, bit 14
71 - A13 o Address bus, bit 13
72 - A12 o Address bus, bit 12
73 - A11 o Address bus, bit 11
74 - A10 o Address bus, bit 10
75 - GND s Ground
76 - +5V s Power supply
77 - A9 o Address bus, bit 9
78 - A8 o Address bus, bit 8
79 - A7 o Address bus, bit 7
80 - A6 o Address bus, bit 6
* Test signals /EA1, /EA2, /EA3, /EAT are missing.
Maybe they are pins 39-42
* Pin 23 seems related BSY, A0, and SX like some strange combination
of the three. Normally not connectedo.
* On a Bloody Wolf PCB, a precision 2.5V reference supply is connected to
VEE for the PSG. This is not used in the PCE and related consoles.
* XOUT is related to XIN but shaped a little differently in terms of the
pulse widths.
HuC6270:
Code: Select all
HuC6270 pin assignments
(C) 2005 Charles MacDonald
WWW: http://cgfm2.emuviews.com
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Overview
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The HuC6270 Video Display Controller (VDC) is a 80-pin QFP in a plastic
package.
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Chip types
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HuC6270 PC-Engine and compatible consoles
DEV-01 Data East rebadged part used in Bloody Wolf
There are 'A' revisions of other components in the C62 chipset, however I
haven't seen a HuC6270A part yet. There may not be one.
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Pin ordering
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64 41
65 +--------+ 40
| |
|. |
80 '--------+ 25
1 24
Pin Signal Description
1 /CS VDC chip select
2 /RD Write strobe
3 /WR Read strobe
4 D15 Data bus, bit 15 (*5)
5 D14 Data bus, bit 14
6 D13 Data bus, bit 13
7 D12 Data bus, bit 12
8 D11 Data bus, bit 11
9 D10 Data bus, bit 10
10 D9 Data bus, bit 9
11 Ground Power supply
12 D8 Data bus, bit 8
13 D7 Data bus, bit 7
14 D6 Data bus, bit 6
15 D5 Data bus, bit 5
16 D4 Data bus, bit 4
17 D3 Data bus, bit 3
18 Vcc Power supply
19 D2 Data bus, bit 2
20 D1 Data bus, bit 1
21 D0 Data bus, bit 0
22 EX8//16 Data bus width select (0= 16-bit, 1= 8-bit) (*5)
23 CK Clock input
24 /RESET Reset input
25 /VSYNC /VSYNC (*2)
26 /HSYNC /HSYNC (*2)
27 DISP Screen blanking status (0= blanked, 1= displayed)
28 SPBG Pixel bus (sprite/background indicator, 1= sprite, 0= background)
29 VD7 Pixel bus (palette value, bit 3)
30 VD6 Pixel bus (palette value, bit 2)
31 VD5 Pixel bus (palette value, bit 1)
32 Vcc Power supply
33 Ground Power supply
34 VD4 Pixel bus (palette value, bit 0)
35 VD3 Pixel bus (pixel value, bit 3)
36 VD2 Pixel bus (pixel value, bit 2)
37 VD1 Pixel bus (pixel value, bit 1)
38 VD0 Pixel bus (pixel value, bit 0)
39 /MWR VRAM write strobe
40 /MRD VRAM read strobe
41 MD0a VRAM data bus, bit 0a (*3)
42 MD1a VRAM data bus, bit 1a
43 MD2a VRAM data bus, bit 2a
44 MD3a VRAM data bus, bit 3a
45 MD4a VRAM data bus, bit 4a
46 MD5a VRAM data bus, bit 5a
47 Vcc Power supply
48 MD6a VRAM data bus, bit 6a
49 MD7a VRAM data bus, bit 7a
50 MD0b VRAM data bus, bit 0b (*3)
51 MD1b VRAM data bus, bit 1b
52 MD2b VRAM data bus, bit 2b
53 MD3b VRAM data bus, bit 3b
54 MD4b VRAM data bus, bit 4b
55 Ground Power supply
56 MD5b VRAM data bus, bit 5b
57 MD6b VRAM data bus, bit 6b
58 MD7b VRAM data bus, bit 7b
59 MA0 VRAM address bus, bit 0
60 MA1 VRAM address bus, bit 1
61 MA2 VRAM address bus, bit 2
62 MA3 VRAM address bus, bit 3
63 MA4 VRAM address bus, bit 4
64 MA5 VRAM address bus, bit 5
65 MA6 VRAM address bus, bit 6
66 MA7 VRAM address bus, bit 7
67 MA8 VRAM address bus, bit 8
68 MA9 VRAM address bus, bit 9
69 MA10 VRAM address bus, bit 10
70 MA11 VRAM address bus, bit 11
71 Ground Power supply
72 Vcc Power supply
73 MA12 VRAM address bus, bit 12
74 MA13 VRAM address bus, bit 13
75 MA14 VRAM address bus, bit 14
76 MA15 VRAM address bus, bit 15 (*4)
77 /IRQ /IRQ output to HuC6280 /IRQ1 input
78 BUSY BUSY status output (*5)
79 A0 Address bus, bit 0
80 A1 Address bus, bit 1
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Notes
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2.) These pins are /HSYNC and /VSYNC, however I don't know which is
which.
Depending on how the VDC is programmed these can be outputs (to
directly drive the sync inputs of a monitor) or inputs (to synchronize
the VDC output with another display generating device, such as the VCE).
3.) The VRAM data bus is 16 bits, however I can't tell which is which
so they are split into two 8-bit buses,'a' and 'b'.
4.) Examples of use:
Bloody Wolf PCB has 128K VRAM, split into two pairs of two 32Kx8
chips. MA15 is /CS for first pair, and inverted MA15 is /CS for the
second pair.
The standard PCE/VCE hardwdare has 64K VRAM, split into one pair
of two 32Kx8 chips. MA15 is /CS for this pair, so access to VRAM above
the 64K boundary results in the chips being disabled and the data
bus is not driven.
5.) I don't have any hardware that uses these pins so their function has
not been confirmed:
D15-D8 : Ordering is guessed based on D7-D0 order.
EX8//16 : Only pin that does not fit the pattern of where other power
supply pins is present; and only 'spare' pin tied to +5V.
Miscellaneous
Signal names are taken from the VDC patents, and are different from those
listed in the Hippodrome schematics page that details the DEV-01 chip.
For example HuC6280 'RDY' is DEV-01 'WAIT'.
In Bloody Wolf, DISP is tied to the CLR input of a latch that outputs
data to the video DAC. This forces the screen to be black when the
display is blanked. This is mainly due to having the color generating
hardware separate from the VDC.
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End
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HuC6260:
Code: Select all
* Need to find mappings for these:
- EX8/16 (HIGH for 8-bit operation, should be +5V)
- CESEL ("output control signal" block diagram says it's an input,
could it be a *display* output enable rather than CPU data bus
output enable?)
- D8 (bidirectional signal, should be N.C.)
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64 41
65 +--------+ 40
| |
|. |
80 '--------+ 25
1 24
Pin Signal Description
1 +5V
2 X21M-IN
3 GND
4 (N.C.)
5 D7
6 D6
7 D5
8 D4
9 D3
10 D2
11 D1
12 D0
13 +5V
14 GND
15 GND
16 +5V
17 Thru C120 (+) 1uF @ 50V to (-) ground
18 Thru C123 (+) 1uF @ 50V to (-) ground
19 GND
20 <Part of C-VIDEO circuit>
21 +5V
22 +5V
23 Thru C126 (+) 1uF @ 50V to (-) ground
24 Thru C125 (+) 1uF @ 50V to (-) ground
25 GND
26 <Part of C-VIDEO circuit>
27 +5V
28 +5V
29 GND
30 Thru C122 (+) 1uF @ 50V to (-) ground
31 Thru C119 (+) 1uF @ 50V to (-) ground
32 GND
33 <Part of C-VIDEO circuit>
34 +5V
35 +5V
36 +5V
37 Thru C124 (+) 1uF @ 50V to (-) ground
38 Thru C121 (+) 1uF @ 50V to (-) ground
39 GND
40 <Part of C-VIDEO circuit>
41 +5V
42 +5V
43 Thru C118 (+) 10uF @ 50V to (-) ground (common w/ p46)
44 C-SYNC
45 +5V
46 Thru C118 (+) 10uF @ 50V to (-) ground (common w/ p43)
47 R-VIDEO
48 GND
49 G-VIDEO
50 +5V
51 B-VIDEO
52 +5V
53 +5V
54 +5V
55 GND
56 GND
57 +5V
58 (N.C.)
59 (N.C.)
60 (N.C.)
61 (N.C.)
62 VD0
63 VD1
64 VD2
65 VD3
66 VD4
67 VD5
68 VD6
69 VD7
70 VD8
71 /H-SYNC
72 /V-SYNC
73 CK
74 A0
75 A1
76 A2
77 /WR
78 /RD
79 /CEK
80 +5V
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End
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HuC6202:
Code: Select all
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Pin assignments
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Hudson HuC6202
80-pin plastic QFP
64 41
65 +--------+ 40
| |
|. |
80 '--------+ 25
1 24
Pin Type Signal Description
1 - i CPU A4 HuC6280 address bus, bit 4
2 - s GND Ground
3 - s +5V Power supply
4 - i CPU A3 HuC6280 address bus, bit 3
5 - i CPU A2 HuC6280 address bus, bit 2
6 - i CPU A1 HuC6280 address bus, bit 1
7 - i CPU A0 HuC6280 address bus, bit 0
8 - i CPU /WR HuC6280 write strobe
9 - i CPU /RD HuC6280 read strobe
10 - i CPU /CE7 HuC6280 /CS for $1FE000-$1FE3FF
11 - i CPU /CEK HuC6280 /CS for $1FE400-$1FE7FF
12 - i CPU SYNC HuC6280 opcode fetch (1= opcode, 0= operand/data)
13 - s GND Ground
14 - b CPU D7 HuC6280 data bus, bit 7
15 - b CPU D6 HuC6280 data bus, bit 6
16 - b CPU D5 HuC6280 data bus, bit 5
17 - b CPU D4 HuC6280 data bus, bit 4
18 - b CPU D3 HuC6280 data bus, bit 3
19 - b CPU D2 HuC6280 data bus, bit 2
20 - b CPU D1 HuC6280 data bus, bit 1
21 - b CPU D0 HuC6280 data bus, bit 0
22 - s +5V Power supply
23 - s GND Ground
24 - o VCE /CS HuC6260 (IC119) /CS
25 - o SA2 Secondary bus, address bit 2 (to IC119)
26 - o SA1 Secondary bus, address bit 1 (to IC104,108,119)
27 - o SA0 Secondary bus, address bit 0 (to IC104,108,119)
28 - i VCE CK HuC6260 (IC119) pixel clock
29 - s GND Ground
30 - i VCE /HSYNC HuC6260 (IC119) horizontal sync
31 - s GND Ground
32 - o VCE VD8 HuC6260 (IC119) video bus, bit 8
33 - o VCE VD7 HuC6260 (IC119) video bus, bit 7
34 - o VCE VD6 HuC6260 (IC119) video bus, bit 6
35 - o VCE VD5 HuC6260 (IC119) video bus, bit 5
36 - o VCE VD4 HuC6260 (IC119) video bus, bit 4
37 - o VCE VD3 HuC6260 (IC119) video bus, bit 3
38 - o VCE VD2 HuC6260 (IC119) video bus, bit 2
39 - o VCE VD1 HuC6260 (IC119) video bus, bit 1
40 - o VCE VD0 HuC6260 (IC119) video bus, bit 0
41 - x (N.C.) Not used (1)
42 - s GND Ground
43 - s +5V Power supply
44 - o /SWR Secondary bus: Write strobe
45 - o /SRD Secondary bus: Read strobe
46 - i VDC #2 VD0 HuC6270 (IC108) video bus, bit 0
47 - i VDC #2 VD1 HuC6270 (IC108) video bus, bit 1
48 - i VDC #2 VD2 HuC6270 (IC108) video bus, bit 2
49 - i VDC #2 VD3 HuC6270 (IC108) video bus, bit 3
50 - i VDC #2 VD4 HuC6270 (IC108) video bus, bit 4
51 - i VDC #2 VD5 HuC6270 (IC108) video bus, bit 5
52 - i VDC #2 VD6 HuC6270 (IC108) video bus, bit 6
53 - i VDC #2 VD7 HuC6270 (IC108) video bus, bit 7
54 - i VDC #2 VD8 HuC6270 (IC108) video bus, bit 8
55 - o VDC #2 /CS HuC6270 (IC108) /CS
56 - o VDC #1 /CS HuC6270 (IC104) /CS
57 - i VDC #1 VD0 HuC6270 (IC104) video bus, bit 0
58 - i VDC #1 VD1 HuC6270 (IC104) video bus, bit 1
59 - i VDC #1 VD2 HuC6270 (IC104) video bus, bit 2
60 - i VDC #1 VD3 HuC6270 (IC104) video bus, bit 3
61 - i VDC #1 VD4 HuC6270 (IC104) video bus, bit 4
62 - s +5V Power supply
63 - s GND Ground
64 - x (N.C.) Not used (1)
65 - i VDC #1 VD5 HuC6270 (IC104) video bus, bit 5
66 - i VDC #1 VD6 HuC6270 (IC104) video bus, bit 6
67 - i VDC #1 VD7 HuC6270 (IC104) video bus, bit 7
68 - i VDC #1 VD8 HuC6270 (IC104) video bus, bit 8
69 - x (N.C.) Not used (1)
70 - s GND Ground
71 - b SD0 Secondary bus: Data bus, bit 0
72 - b SD1 Secondary bus: Data bus, bit 1
73 - b SD2 Secondary bus: Data bus, bit 2
74 - b SD3 Secondary bus: Data bus, bit 3
75 - b SD4 Secondary bus: Data bus, bit 4
76 - b SD5 Secondary bus: Data bus, bit 5
77 - b SD6 Secondary bus: Data bus, bit 6
78 - b SD7 Secondary bus: Data bus, bit 7
79 - i MODE VPC operating mode (0= PCE mode, 1= SGX mode) (2)
80 - i /RESET Reset input
1.) Function of N.C. pins are unknown. In the SuperGrafx they are not
connected to anything.
2.) The MODE pin should either be tied to ground or to +5V through a
pull-up resistor.
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End
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Don't forget your two NOPs after CSH.