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VRAM -> VRAM DMA

Posted: Tue Aug 19, 2008 8:43 pm
by Xavier
Hello I have 2 questions:

1- Do somebody know what happen when you launch a vram to vram dma transfert immediately (well actually some cycle after) after another one?
I know the dma adresse registers act as counter during dma transfert so logically trouble must/can occur...
However I simulated parallax using dma and my display is not corrupted, a good surprise but I would like to be sure.

2- Is dma speed dependant of the VCE pixel clock? If I tweak $400 bit 0 and 1 VCE reg during vblank (and restore is befor the vsync end in order to not destroying my display) to switch from 5 to 7 or 10Mhz did my dma'll be quicker?

Re: VRAM -> VRAM DMA

Posted: Tue Aug 19, 2008 9:23 pm
by Charles MacDonald
I can only answer #2:

YES! ;D

The DMA is greatly sped up when you go into 7.16 MHz or 10.73 MHz mode. I wrote a program that simulated vertical column scrolling using VRAM to VRAM DMA, and the number of scanlines used during the transfer went from 20 or so with $0400=$04 to about 3 with $0400=$06. A dramatic improvement.

The same thing applies to VRAM writes and any kind of VDC access in general. The pixel clock directly controls the VDC, so the VDC runs faster and can process DMA and VRAM access quicker at the higher clock rates. Note that the +1 cycle overhead for writing to the $FF:$0000-$03FF range is unchanged as the CPU causes that, not the VDC. But any VDC-generated delays will be shorter.

The only difficulty is ensuring you have the right VDC CRTC registers set up when you change clock modes. I also found there was some jitter when switching between 320-pixel mode for my display, and 512-pixel mode during vblank. There are no problems switching between 256 and 512 pixel mode, probably because they are multiples of each other in terms of timing.

Re: VRAM -> VRAM DMA

Posted: Wed Aug 20, 2008 6:58 pm
by Xavier
Today I found a response to my first question, the VDC seem to allow some data to be transfered, but not much something like 250/300 words.
If to much dma transfert are required without pause, the destination graphic are eventually corrupted.

For the second point, well Charles it's a good news!
BTW about the glitch when you switch 320/512 resolutions, I found than just tweaking the VCE reg at $400 during vsync and without altering VDC display parameter seem to don't jam the video, but it need more test to confirm.

Edit:
Eventually tried it on true hardware, it work but the display is unstable, certainly jam the synchro pulse and most TV set don't appreciate it :(