Fun with BSY

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Charles MacDonald
Posts: 38
Joined: Sun Jun 22, 2008 5:18 pm
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Fun with BSY

Post by Charles MacDonald »

So at some point you probably have asked yourself what the BSY flag is for in the status register. The CPU already gets halted by the VDC when waiting for a chance to access VRAM, so having a busy flag seems redundant. I think this is how it works.

When the VDC writes data to $0003, the entire word (previously latched value from $0002 and newly written data to $0003) is stored temporarily. The VDC waits for a CPU access slot, based on the VRAM dot width settings. Once it has one, the data is stored and MAWR is incremented.

During this time that the VDC is waiting, BSY is set. If you try to write again, the latch is already full so the VDC asserts /RDY and halts the 6280 during the write cycle until the first word can be stored.

How to prove this? There are a few situations were this came up:

1. I tried filling VRAM by writing a word to VRAM and triggering VRAM to VRAM DMA. The fill data was always wrong unless I either inserted a delay (nops) or polled BSY until it was clear. This case in particular shows that the CPU isn't halted during the 1st write and that you can't expect VRAM to be updated immediately after writing to $0003.

2. One program I disassembled polled BSY before changing the increment size bits in CR. If there was a VRAM write pending and you changed the IW bits, the wrong auto-increment value would be applied once that data was finally committed to VRAM and MAWR was adjusted. So polling it there prevents that from happening.

3. If you set the dot width to %11, there are no CPU slots during the active display. Correspondingly, writing to VRAM halts the CPU for exactly one scanline, until horizontal blanking when the CPU has a few more slots.

When do you need to worry about BSY? Probably never, there are just a few situations:

1. Changing IW bits of CR right after writing to $0003
2. Triggering DMA right after writing to $0003, assuming DMA reads from the VRAM location you wrote

There may be another case where you have MARR and MAWR set up so that you write to $0003 and read it back from $0003. This is pointless, but if you did it and the CPU didn't get halted by the VDC, you'd need to poll BSY. I haven't investigated how the CPU is affected by VRAM reads, so this part is unclear.
Don't forget your two NOPs after CSH.
iskk
Posts: 4
Joined: Tue Aug 12, 2008 6:28 am

Re: Fun with BSY

Post by iskk »

This is actually very interesting :-)
I'm going to setup a PCE test bench and post my results.
Thanks for sharing your findings!
-Ki
Charles MacDonald
Posts: 38
Joined: Sun Jun 22, 2008 5:18 pm
Contact:

Re: Fun with BSY

Post by Charles MacDonald »

iskk wrote:This is actually very interesting :-)
I'm going to setup a PCE test bench and post my results.
Thanks for sharing your findings!
-Ki
FWIW, I can't get point #3 to work reliably. Sometimes it delays for a scanline, sometimes it doesn't. The only thing that works consistently is the need to poll BSY after a VRAM write, before you trigger VRAM to VRAM DMA.

Nice to see you here!
Don't forget your two NOPs after CSH.
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